A Technique for Efficient Evaluation of SRAM Timing Failure
نویسندگان
چکیده
This paper presents a technique to evaluate the timing variation of SRAM. Specifically, a method called loop flattening that reduces the evaluation of the timing statistics in the complex, highly structured circuit to that of a single chain of component circuits is justified. To then very quickly evaluate the timing delay of a single chain, a statistical method based on Importance Sampling augmented with targeted, high-dimensional, spherical sampling can be employed. The overall methodology has shown 650X or greater speed-up over the nominal Monte Carlo approach with 10.5% accuracy in probability. Examples based on both the large-signal and small-signal SRAM read path are discussed and a detailed comparison with state of the art accelerated statistical simulation techniques is given.
منابع مشابه
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing
A novel area-efficient dual replica-bitline delay technique is proposed in this brief to improve process-variation-tolerance of low voltage SRAM application. This strategy suppresses the timing variation by adding one another replica-bitline and introducing novel replica cell which has the same size as conventional. Simulation results in TSMC 65nm LP technology show that more than 32.3% timing ...
متن کاملEnergy Efficient Novel Design of Static Random Access Memory Memory Cell in Quantum-dot Cellular Automata Approach
This paper introduces a peculiar approach of designing Static Random Access Memory (SRAM) memory cell in Quantum-dot Cellular Automata (QCA) technique. The proposed design consists of one 3-input MG, one 5-input MG in addition to a (2×1) Multiplexer block utilizing the loop-based approach. The simulation results reveals the excellence of the proposed design. The proposed SRAM cell achieves 16% ...
متن کاملLoop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis
The impact of process variation in deep-submicron technologies is especially pronounced for SRAM architectures which must meet demands for higher density and higher performance at increased levels of integration. Due to the complex structure of SRAM, estimating the effect of process variation accurately has become very challenging. In this paper, we address this challenge in the context of esti...
متن کاملA Sub-threshold 9T SRAM Cell with High Write and Read ability with Bit Interleaving Capability
This paper proposes a new sub-threshold low power 9T static random-access memory (SRAM) cell compatible with bit interleaving structure in which the effective sizing adjustment of access transistors in write mode is provided by isolating writing and reading paths. In the proposed cell, we consider a weak inverter to make better write mode operation. Moreover applying boosted word line feature ...
متن کاملSelf-Timed SRAM with Smart Latency Bundling Self-Timed SRAM with Smart Latency Bundling
In energy-aware design, especially for systems with uncertain power sources, asynchronous computation loads which can function under variable power supply have many potential advantages. Fully safe asynchronous loads based on delay insensitivity (DI), however, tend to suffer power and size penalties. As a compromise, delay bundling has been widely used in asynchronous computation, but tradition...
متن کامل